(1) Field of the Invention
The invention relates to output buffer circuits, and more particularly to an advanced output buffer for static memories in which a fast output buffer is required.
(2) Description of the Related Art
Workers in the field have made various attempts to increase the speed of static RAM (Random Access Memory) devices. Kertis et al U.S. Pat. No. 4,926,383 describes a BiCMOS static RAM (random access memory)in which a bipolar transistor is used to clamp a memory bit line to an intermediate voltage to decrease the access time of the static RAM. Bell U.S. Pat. No. 4,975,877 reduces the access time for read operations by several circuit implementations. Sawada et al U.S. Pat. No. 4,984,208 provides a control circuit for refreshing storage data within a read/write cycle, and shows an input/output circuit 55 which provides an intermediate voltage during those periods when active data is not present. Hamano et al U.S. Pat. No. 5,091,889 for a static RAM describes the use of an intermediate voltage for a bit line, in order to prevent write errors. In the latter two references, an intermediate voltage is used at a circuit output for various reasons.